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Home > Press Releases > Mixel, Rambus and Hardent Collaborate to Deliver State-of-the-Art Integrated MIPI Display Subsystem Solution

Mixel, Rambus and Hardent Collaborate to Deliver State-of-the-Art Integrated MIPI Display Subsystem Solution

Highlights: 

  • Leaders in MIPI® technology join forces to offer a complete display subsystem solution with best-in-class bandwidth efficiency
  • Integrated solution includes PHY, digital controller and VESA Display Stream Compression (DSC) to deliver maximum MIPI DSI-2SM functionality and operational modes
  • Proven, reusable IP solution lowers implementation risk and accelerates time to market
  • Solution enables higher resolutions and frame rates for mobile, AR/VR and automotive display applications

SAN JOSE, CA, and MONTREAL, QC – March 10, 2021 – Mixel, Inc., a leading provider of mixed-signal IPs, Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, and Hardent, Inc., a leading provider of video compression IP cores, announced a state-of-the-art solution for next-generation displays. This integrated solution brings together the IP of the three MIPI® Alliance member companies enabling rapid deployment of mobile, AR/VR and automotive displays leveraging MIPI DSI-2 technology. This optimized solution is available immediately and includes:

Targeting display applications requiring high bandwidth and excellent power efficiency, this subsystem solution brings a significant improvement in overall throughput available with DSI-2. This level of integration using proven, broadly adopted IP sets a new benchmark for performance, ease of implementation, and time to market.

“We are excited to announce the combined solution with our Mixel MIPI Central partners, Rambus and Hardent, to fill a gap in the MIPI ecosystem,” said Justin Endo, marketing manager at Mixel. “Side-by-side instances of our latest generation of C-PHY/D-PHY combo IP support over 60 Gbps aggregate bandwidth without compression, but with it, we can support up to three times that, enabling state-of-the-art performance, and future-proofing our customers’ designs for years to come.”

“The Rambus fully configurable, high-performance DSI-2 Host and Peripheral Controller cores have been fully integrated, verified and delivered with the Mixel PHY and Hardent DSC, enabling customers to quickly create state-of-the-art display designs,” said Joe Rodriguez, product marketing manager at Rambus.

“We are very pleased to launch this new display IP subsystem with our partners Mixel and Rambus,” says Alain Legault, VP of IP products at Hardent. “Hardent’s DSC IP cores have been fully integrated and verified with the Mixel PHY and Rambus controller IP, giving customers the confidence to leverage the advantages of DSC video compression, all while saving vital time during the design cycle.”

Benefits of the Mixel-Rambus-Hardent MIPI DSI-2 Solution

  • Optimized for ASIC design performance (PPA)
  • Maximized functionality and availability of all MIPI DSI-2 operating modes
  • Lower project risk with a fully integrated and verified IP solution
  • Accelerate ASIC and SoC time to market

Technical Details
Mixel’s MIPI C-PHY/D-PHY combo IP is a high-frequency, low-power, low-cost, physical layer. It can be configured as a MIPI transmitter or receiver, supporting both the camera interface MIPI CSI-2® v3.0 and display interface DSI-2 v1.1 and is backward compatible with previous generations of each specification. In C-PHY mode, Mixel’s MIPI C-PHY v2.0 supports a speed of 4.5 giga-symbols per second (Gsps) per trio which is an equivalent data rate of 10.26 Gbps/trio. In D-PHY mode, the IP supports speeds up to 4.5 Gbps per lane and complies with the MIPI D-PHY v2.5 specification. With up to three trios in C-PHY and up to four lanes in the D-PHY, the combo IP reaches an aggregate bandwidth of 30.78 Gbps and 18 Gbps in their respective modes.

The Rambus DSI-2 Controller cores are DSI-2 v1.1 compliant and optimized for high performance, low power and small size. The cores are full featured supporting host (Tx) and peripheral (Rx), multiple user interface options, and are highly configurable. 64 and 32-bit core widths are available enabling the user to make clock rate versus size tradeoffs.

Hardent’s VESA Display Stream Compression (DSC) IP cores are designed for use in cutting-edge display applications where visually lossless, ultra-low latency compression is required. DSC video compression increases overall transmission bandwidth on the MIPI DSI-2 transport interface by up to 3X, allowing designers to free up the bandwidth needed to create displays with higher resolutions, faster refresh rates, and greater color depths.

Webinar
For more information about the Mixel, Rambus and Hardent IP subsystem, register now to attend the webinar, “Next-Generation Displays: An Integrated IP Solution from Mixel, Rambus and Hardent” presented by the three companies on April 7th at 11:00am Pacific Time.

Availability
The Mixel, Rambus, and Hardent MIPI DSI-2 / VESA DSC subsystem solution is available today in both host (TX) and peripheral (RX) versions.

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