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Rambus silicon-proven, high-performance PCI Express® (PCIe®) 6.1, 5.0, 4.0 and earlier generation digital controllers are optimized for use in SoCs, ASICs and FPGAs. These market-leading solutions for high-performance interfaces address AI/ML, data center and edge applications.
Version | Maximum Data Rate (GT/s) | Controller | Controller with AXI |
---|---|---|---|
PCIe 6.1 | 64 | Product Brief | Product Brief |
PCIe 5.0 | 32 | Product Brief | Product Brief |
PCIe 4.0 | 16 | Product Brief | Product Brief |
PCIe 3.1 | 8 | Product Brief | Product Brief |
PCIe 2.1 | 5 | Product Brief | Product Brief |
Feature | PCIe 6.1 Controller | PCIe 5.0 Controller | PCIe 4.0 Controller | PCIe 3.1 Controller | PCIe 2.1 Controller |
---|---|---|---|---|---|
Data Rate (GT/s) | 64 | 32 | 16 | 8 | 5 |
Data Path | Scalable | Scalable | Scalable | Scalable | Scalable |
Topologies Supported | Root Port Endpoint Switch Port Dual-Mode | Root Port Endpoint Switch Port Dual-Mode | Root Port Endpoint Switch Port Dual-Mode | Root Port Endpoint Switch Port Dual-Mode | Root Port Endpoint Switch Port Dual-Mode |
Duplex Lane Configurations | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 | x1, x2, x4, x8, x16 |
Backward Compatibility | 5.0, 4.0, 3.1/3.0 | 4.0, 3.1/3.0 | 3.1/3.0 | 3.0/2.1/2.0 | 1.1/1.0 |
Clock Gating/Power Gating | Yes | ||||
Advanced RAS | Yes | Yes | Yes | Yes | Yes |
Virtual Channel Support | FLIT and non-FLIT mode | ||||
Forward Error Correction (FEC) | Yes | ||||
L0p Low Power Mode | Yes | ||||
Optional Features | IDE Security, AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink | AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink | AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink | AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink | AER, ECRC, ECC, MSI, MSI-X, Multifunction, Crosslink P2P |
Solution | Product Brief | Description |
---|---|---|
PCIe 6.0 Retimer Controller | PCIe 6.0 Retimer Controller with CXL Support Provides Highly Optimized, Low-latency Data Path for Signal Regeneration | |
PCIe 5.0 Multi-port Switch | Customizable Multi-port Switch, Connects One Upstream Port to Up to 31 Downstream Ports | |
PCIe Controller for USB4 | PCIe 5 Controller with USB4 Support, with Native Logic Interface Options | |
PCIe Controller for USB4 with AXI | PCIe 5 Controller with USB4 Support, with AXI Logic Interface Options | |
PCIe Switch for USB4 | Customizable Switch with USB4 Support, Connects One Upstream Port to Up to 31 Downstream Ports |
Solution | Product Brief | Description |
---|---|---|
INSPECTOR for PCIe 5.0 | Interposer Card for Diagnostic Testing, Exercising and Debug of PCIe Devices at up to 32 GT/s | |
Gen5HOST | Host Enabling Reference Platform for Prototyping and Development of PCIe 5.0 Devices and Apps | |
Gen5ENDPOINT | Endpoint Reference Platform for Prototyping and Development of PCIe 5.0 Devices | |
XpressAGENT | Add-on Core Simplifies Observability and Expedites Debugging of PCIe and CXL subsystems |
Rambus provides integration and validation of the PCIe 6.1 digital controller with the customer’s choice of 3rd-party PCIe 6.1 PHY.
The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the rapid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.