
Powering the Next Wave of AI Applications
Artificial Intelligence/Machine Learning (AI/ML) grows at a blistering pace. The size of the largest training models has passed 100 billion parameters and is on pace
Home > Memory PHYs > Page 2
Artificial Intelligence/Machine Learning (AI/ML) grows at a blistering pace. The size of the largest training models has passed 100 billion parameters and is on pace
Frank Ferro, Senior Director Product Management at Rambus, has written a detailed article for Semiconductor Engineering that explains why HBM2E is a perfect fit for
Rambus’ Suresh Andani has written a detailed Semiconductor Engineering article that explores how PCIe 5 can effectively accelerate AI and ML applications. According to Andani,
HiPEAC, a European network of almost 2,000 world-class computing systems researchers, named Matthias Jung (Fraunhofer IESE), Lukas Steiner, and Norbert Wehn (TUK) as winners of
The Rambus’ CSI-2 Tx/Rx Controller Cores and DSI-2 Host/Peripheral Cores with support of up to 2.5 Gbps/lane is available with the LogiCORE D-PHY on Kintex
Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of