Complete Memory Interface Solution for HBM2E Launched
Rambus has announced a comprehensive interface solution for HBM2E memory consisting of co-verified PHY and memory controller. Operating at a top speed of 3.2 Gbps
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Rambus has announced a comprehensive interface solution for HBM2E memory consisting of co-verified PHY and memory controller. Operating at a top speed of 3.2 Gbps
In part one of this series, we discussed how the world’s digital data is growing exponentially, doubling approximately every two years. In fact, there’s so
Written by Steven Woo for Rambus Press There has been quite a lot of recent news about domain-specific processors that are being designed for the
In part one of this two-part blog series, Steven Woo, Rambus fellow and distinguished inventor, spoke with Ed Sperling of Semiconductor Engineering about utilizing various
Steven Woo, Rambus fellow and distinguished inventor, recently spoke with Ed Sperling of Semiconductor Engineering about how certain number formats can help system designers optimize
Earlier this month, Semiconductor Engineering editor-in-chief Ed Sperling hosted an industry roundtable to discuss new DRAM options and considerations. Frank Ferro, our senior director of