SerDes signal integrity challenges at 28Gbps and beyond
Maintaining signal integrity has become increasingly difficult for SerDes designers at 28Gbps, 56Gbps and beyond. After nearly fifty years, NRZ technology continues to pose significant
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Maintaining signal integrity has become increasingly difficult for SerDes designers at 28Gbps, 56Gbps and beyond. After nearly fifty years, NRZ technology continues to pose significant
Samsung Electronics has announced a successful network processor tape-out based on the company’s 14LPP (Low-Power Plus) process technology in close collaboration with eSilicon and Rambus.
Last week, we announced the launch of our 56G Multi-protocol SerDes (MPS) PHY developed on second-gen FinFET (Fin Field Effect Transistor) process technology. With a
Rambus has announced a 56G Multi-protocol SerDes (MPS) PHY developed on second-gen FinFET (Fin Field Effect Transistor) process technology to meet the evolving demands of
The DesignCon 2017 expo kicks off on February 2nd in Santa Clara. We’re at booth #833, showcasing our comprehensive suite of Ethernet, PCIe and DDRn
Ed Sperling of Semiconductor Engineering notes that power has always been a “global concern” in the design process because it affects every part of a chip.