Rambus’ Smart Data Acceleration (SDA) research platform focuses on architectures designed to offload computing closer to very large data sets at multiple points in the memory and storage hierarchy. Potential use case scenarios include real-time risk analytics, ad serving, neural imaging, transcoding and genome mapping.
Image Credit: Patrick Moorhead, Moor Insights and Strategy
Comprising software, firmware, FPGAs and significant amounts of memory, the platform operates as an effective test bed for new methods of optimizing and accelerating analytics in extremely large data sets. As such, the SDA’s versatile combination of hardware, software, firmware, drivers and bit files can be precisely tweaked to facilitate architectural exploration of specific applications.
Simply put, the SDA – powered by an FPGA paired with 24 DIMMS – offers high memory densities linked to a flexible computing resource.
“This form factor enables a higher density of DIMM sockets than typical servers in use today,” a recently published white paper written by Moor Insights & Strategy researchers explained. “And because these are standard DIMM sockets, other DIMM-based technologies can be supported by the architecture, such as NAND and emerging storage class memories.”
Image Credit: Patrick Moorhead, Moor Insights and Strategy
At the system level, one or more SDA engines can be combined into a flexible platform. The engines are also configurable (or recognized) as specific types of devices, such as ultra-fast block storage, a Key/Value store, or a caching device.
“When configured as an ultra-fast block storage device, initial tests show that higher IOPS rates can be achieved under certain workloads, and with much better latency under load, compared to state-of-the-art NVMe SSDs,” the researchers confirmed. “To date, only a limited number of benchmarks have been run, but results are in line with expectations. Notably, in 4KB random access tests, the SDA engine can deliver up to 1M IOPS with latency under load in the 10 μs to 60 μs range for both reads and writes, with additional headroom to achieve higher IOPS rates.”
Image Credit: Patrick Moorhead, Moor Insights and Strategy
As the Moor Insights & Strategy researchers note, the overarching purpose of the SDA research lies in the collection of FPGAs at the heart of the design – where each FPGA has parallel and independent access to the DIMMs. The SDA engines are also “semantically-aware,” meaning structures in memory can be described to the SDA and bounded.
“These structures can then be operated on or subjected to transformations in a fashion that maximizes parallelism and efficiency – without the need to move data,” the researchers explained. “In effect, this creates a unique data store that can offload significant data operations from the main processor and into the SDA engine, which essentially operates as a large data-parallel coprocessor.”
Currently, the SDA’s base extensible command set is targeted at accelerating and offloading the transformation of common data structures such as those found in Big Data analytics applications. However, the Smart Data Acceleration platform could ultimately be made available over a network where it would serve as a key offload agent in a more disaggregated scenario.
“This type of semantically aware data transformer holds great promise. Such a resource could be applied to modern applications and address the challenges highlighted in the hierarchy off-load gap,” the analysts concluded.
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