Chiplets keep the scaling of integrated circuits (ICs) rolling

As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more complex system on chips (SoCs). This is particularly true at a time when our old friend Moore’s Law has lost a step.

However, as the complexity of SOCs increases, so do the costs to manufacture in leading-edge FinFET geometries. As misery loves company, achieving first-time-right silicon has become more difficult as well. Additionally, there are greater challenges for power scaling and yield. In other words, everything gets harder.

Chip disaggregation, or chiplets, offers an alternative to the traditional monolithic SoC scaling approach. Aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields.

For applications like artificial intelligence (AI), where there is a “Cambrian explosion” in the number of SoCs and architectural approaches under development, chiplets are an ideal solution. Greater experimentation, and faster time to market are possible when a designer can revise a single chiplet as opposed to having to re-spin an entire SoC.

A key enabling technology required to make chiplet performance on par with that of an SoC is the high-speed interconnects between the chiplets. These must run at extremely high data rates and at very low power.

The Optical Internetworking Forum (OIF) specified the Common Electrical I/O (CEI) 112G XSR (Extra Short Reach) interface to provide the interconnect between chiplets, and between chiplets and optical engines. It is designed for low complexity and very low power while offering extremely high throughput capabilities.

Today, we announced the Rambus 112G XSR SerDes on 7nm FinFET process is now available for licensing. It joins a portfolio of 7nm Rambus PHY solutions including GDDR6, HBM2 and 112G LR (Long Reach) tailored for advanced applications such as AI, advanced driver-assistance systems (ADAS) and hyperscale data centers. With these interface solutions, chip designers can satisfy their need for speed and unleash the power of new compute architectures.