In planning for DDR5, the industry laid out ambitious goals for memory bandwidth and capacity while aiming to maintain power within the same envelope on a per module basis. In order to achieve these goals, DDR5 required a smarter DIMM architecture; one that would embed more intelligence in the DIMM and increase its power efficiency. One of the largest architectural changes of this smarter DIMM architecture was moving power management from the motherboard to an on-module Power Management IC (PMIC) on each DDR5 RDIMM.
This change followed the trend in microelectronic systems, that to optimize power, it’s best to deliver as high a voltage as possible to the endpoint where the power is consumed. Then at the endpoint, regulate that incoming high voltage into the lower voltages with higher currents required by the endpoint components.
In previous DDR generations, the regulator was on the motherboard, and it had to deliver a low voltage at high current across the motherboard, through a connector and then onto the DIMM. As supply voltages were reduced over time (to maintain power levels at higher data rates), it was a growing challenge to maintain the desired voltage level because of IR drop. By implementing a PMIC on the DDR5 RDIMM, the problem with IR drop was essentially eliminated.
In addition, the on-DIMM PMIC allows for very fine-grain control of the voltage levels supplied to the various components on the DIMM. As such, DIMM suppliers can really dial in the best power levels for the performance target of a particular DIMM configuration.
The upshot is that power management has become a major enabler of increasing memory performance. Advancing memory performance has been the mission of Rambus for nearly 35 years. We’re intimate with memory subsystem design on modules, with expertise across many critical enabling technologies, and have demonstrated the disciplines required to successfully develop chips for the challenging module environment with its increased power density, space constraints and complex thermal management.
As part of the development of our industry-leading DDR5 memory interface chipset, and given our heritage and mission, Rambus built a world-class power management team and has now introduced a new family of best-in-class DDR5 server PMICs. This new server PMIC product family lays the foundation for a roadmap of future power management chips. As AI continues to expand from training to inference, increasing demands on memory performance will extend beyond servers to client systems and drive the need for new PMIC solutions tailored for emerging use cases and form factors.
We recently sat down with John Eble, vice president of product marketing for Rambus Memory Interface Chips, to learn more about DDR5 module technology including PMICs. Watch the video below:
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