The DesignCon 2016 expo kicked off on January 20th in Santa Clara. Rambus was at booth #835, showcasing its R+™ enhanced standard serial link and memory IP core solutions, along with tools for server, mobile and networking applications.
Rambus also hosted a full-day training session. The workshop explored industry trends and challenges including the shifting bottlenecks in future high-performance system design; how high-speed serial links are shaping future networking and enterprise systems; and key architecture considerations for high-speed serial link interface design and implementation.
In addition, Rambus scientists and engineers hosted the following conference tracks on Wednesday and Thursday:
Keynote: Silicon Foundations for Security – Paul Kocher, Chief Scientist, Cryptography Research Division of Rambus
Room: Mission City Ballroom
Date: Thursday, January 21
Time: 12:00pm – 12:45pm
Pass Type: All Access, Alumni All Access Pass, 2-Day Pass, Expo Pass
The security capabilities and limitations of chips play a critical role in security. Unfortunately, these foundations typically assume complex software will be bug-free. As a result, security failures are increasingly common in today’s complex and inter-connected products.
Paul Kocher, founder of Cryptography Research, explored the intersections of cryptography and data security with chip architectures. Power analysis attacks were used as an example of how layers of abstraction can conceal security challenges. The talk also explored architectures aimed at scaling more securely, including on-chip hardware security solutions for SoCs and infrastructure needs for the manufacturing and management of complex connected devices.
Analysis, Modeling and Characterization of Multi-Protocol High-Speed Serial Links – Wendem Beyene, Technical Director
Room: Ballroom GH
Date: Wednesday, January 20
Time: 9:20am – 10:00am
Track: 08 Optimize High Speed Design
Pass Type: All Access, Alumni All Access Pass, 2-Day Pass
Improved analysis, modeling, characterization and correlation methods of multi-protocol high-speed transceivers that utilize T-coil to enhance the transmitter and receiver bandwidth, transmitter FIR filters and receiver CTLE and DFE equalizers was presented.
The key circuit blocks were measured and modeled using IBIS-AMI models and the overall system performance including the eye diagrams, BER curves are well correlated to on-die measurements. The paper discussed the procedure taken to model, measure, and verify the high-speed transceivers meet the standard specifications such as return loss, jitter tolerance, BER and convergence of the adaptation equalizers and CDR to optimize the margins for various channels.
Rethinking System Architectures: The Shifting Performance Bottlenecks Driving Future Silicon Design – Steven Woo, VP, Solutions Marketing and Distinguished Inventor
Room: Great America 3
Date: Wednesday, January 20
Time: 9:20am – 10:00am & 2:00pm – 2:40pm
Moore’s Law has relentlessly delivered tremendous improvements in processing performance and functionality for several decades, enabling newer generations of processors to surpass the capabilities of their predecessors. While processors will continue to become more feature-rich, the emergence of new computing paradigms and slower rates on improvement in other areas mean that power and performance bottlenecks moving away from processors into others subsystems.
Moving data between processing elements, memory, storage, and across networks is becoming a growing challenge, and concerns about power and security are forcing chip and system architects to rethink not only how silicon needs to be architected, but systems as a whole. In this talk, I discussed how these concerns are driving changes in the way we think about both silicon and systems in the future.
Which SerDes To Choose: System Tradeoffs For High-speed Serial Link Selection – Mohit Gupta, Director, Product Marketing, Rambus.
Room: Great America 3
Date: Wednesday, January 20
Time: 10:15am – 10:55am & 2:50pm – 3:30pm
With the new era of every device getting smart and data getting bigger, there has been a constant increase in bandwidth and speed requirements for networking communications on the back end side. From the age of chips communicating at 1Gbps to 10Gbps to 40Gbps to 100Gbps and setting the stage for 400Gbps and 1Tbps in coming years, everyone wants to communicate faster and faster but at the same time by being more efficient (energy consumption) and smaller (silicon area).
With the new technology nodes trending in even faster than Moore’s law, there are variety of dimensions and tradeoffs which are required to define a Serial link for the next generation needs to make a particular solution effective on all fronts.
Interested in learning more about Rambus @ DesignCon 2016? You can check out our official conference page here.
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