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The Rambus Client Clock Driver (CKD) enables DDR5 CUDIMMs and CSODIMMs operating at up to 7200 MT/s. Client DIMMs at 6400 MT/s and above employ a CKD as part of their standard architecture to manage jitter and close timing for the synchronous memory system.
The Rambus DDR5 CKD buffers the clock between the host controller and the DRAMs on DDR5 CUDIMMs and CSODIMMs. In Single PLL mode, the device uses one input clock pair to produce four separate output clock pairs for the two DRAM channels on the DIMM. In Dual PLL mode, the device uses two input clock pairs to produce four separate output clock pairs to the two DRAM channels. In PLL Bypass mode, the device uses two input clock pairs to produce four separate output clock pairs to the DRAM channels.
Driven by a confluence of megatrends, global data traffic is increasing at an exponential rate. For example, 5G networks are enabling billions of AI-powered IoT devices untethered from wired networks. Nowhere is the impact of all this growth being felt more intensely than in data centers. Indeed, hyperscale data centers have become the critical hubs of the global data network. DDR5 DRAM will enable the next generation of server systems providing the massive computing power of hyperscale and enterprise data centers. Learn about the benefits of DDR5 memory and the design considerations for implementing DDR5 DIMMs.