Rambus @ DesignCon 2025

Technology Advancements for AI in the Data Center

Speaker: Dr. Steven Woo, Fellow and Distinguished Inventor, Rambus
Abstract: AI continues to evolve at a lightning pace, with generative AI powered by sophisticated Large Language Models exceeding one trillion parameter sizes.
Incredible amounts of data must be processed, moved and secured to train these models and the even larger ones on the horizon. Join Rambus Fellow and Distinguished Inventor, Dr. Steven Woo, as he discusses the memory, interface and security technologies critical to powering advanced computing for AI.

Accelerating AI Workloads with Composable Memory and Hardware Acceleration

Speakers: Lou Ternullo, Senior Director of Product Marketing, Rambus; Klas Moreau, CEO, ZeroPoint Technologies; Yiannis Nikolakopoulos, Software Lead, ZeroPoint Technologies
Abstract: The increasing demand for AI and machine learning applications drives the need for high-performance, low-latency memory solutions. This session presents a novel approach to integrating composable memory solutions with AI and caching services. By leveraging Rambus CXL IP and hardware-accelerated compression IP in a fully assembled controller prototype FPGA system, we demonstrate significant performance improvements for real-world workloads such as Meta Cachelib, a widely used hyperscale caching application for AI services.

Join Lou Ternullo from Rambus along with Klas Moreau and Yiannis Nikolakopoulos from ZeroPoint as they discuss a solution that addresses the evolving requirements of hyperscale data centers, as outlined in open compute specifications. By combining the flexibility of CXL with the efficiency of hardware acceleration, we enable efficient data movement, compression, and decompression, reducing system latency and power consumption. We present detailed performance benchmarks and analysis, highlighting the benefits of our approach in terms of throughput, latency, and energy efficiency.

Meeting Automotive Design, Safety and Security Challenges with an Integrated HSM Solution

Speakers: Omar Alshabibi, Lead Global Product Manager for Cyber Security and Software-defined Vehicles, ETAS; Raj Uppala, Senior Director of Marketing & Partnerships, Rambus
Abstract: The automotive industry is undergoing a transformative shift towards the software-defined vehicle (SDV) bringing a broad set of implementation challenges. Revolutionary approaches are needed to navigate the ever-increasing complexity, support faster time-to-market demands, and meet regulatory safety and security compliance. Join Omar Alshabibi of ETAS and Raj Uppala of Rambus as they discuss an innovative integrated HSM solution that combines synthesizable Hardware Security Module (HSM) hardware IP with pre-integrated, pre-validated HSM software to meet the needs of automotive OEM and SoC developers.

Unleashing the Performance of AI Training with HBM4

Speakers: Kevin Yee, Sr. Director of IP and Ecosystem Marketing, Samsung Foundry; Nidish Kamath, Director of Product Management for Memory Interface IP, Rambus
Abstract: AI training models are growing in both size and sophistication at a breathtaking rate, requiring ever greater bandwidth and capacity. With its unique 2.5D/3D architecture, HBM4 can deliver Terabytes per second of bandwidth and unprecedented capacity in an extremely compact form factor. Join Kevin Yee from Samsung and Nidish Kamath from Rambus discuss the design considerations of HBM4 memory subsystems (PHY, Memory Controller, and Packaging) in next-generation AI SoCs.

GDDR Memory for High-Performance AI Inference

Speaker: Nidish Kamath, Director of Product Management for Memory Interface IP, Rambus; Frank Ferro, Group Director Memory and Storage IP, Cadence Design Systems
Abstract: The rapid rise in size and sophistication of AI/ML inference models requires increasingly powerful hardware deployed at the network edge and in endpoint devices. AI/ML Inference workloads for applications like edge computing and Advanced Driver Assistance Systems (ADAS) require high bandwidth memory while keeping costs low. With performance of over 20 Gbps, GDDR6 has been a good solution, providing an excellent combination of high bandwidth and cost efficiency.

As bandwidth requirements increase, the recently released GDDR7 with speeds of 36 Gbps, will provide the additional bandwidth needed moving forward for these systems. To implement high-speed memory interfaces for both the memory PHY and controller, it requires the performance and power efficiency of TSMC’s advanced process nodes. This presentation will discuss how Rambus and Cadence worked together to develop an integrated memory subsystem that is deployed widely in end-customer systems using TSMC advanced nodes. Also discussed will be the signal integrity challenges of implementing GDDR6 and GDDR7 at these high data rates.

Next-Gen Memory Unlocked: HBM4 and LPDDR5/5X Verification for High-Performance Computing

Speakers: Nidish Kamath, Director of Product Management for Memory Interface IP, Rambus; Gordon Allan, Product Manager for Verification IP, Siemens EDA
Abstract: High Bandwidth Memory (HBM) has transformed AI, machine learning, and high-performance computing (HPC) by addressing data transfer bottlenecks and boosting performance. The upcoming HBM4 standard takes this further, offering unprecedented speeds to support faster AI model training and execution. Similarly, LPDDR5/5X, the next-generation Low Power Double Data Rate memory, sets a new benchmark with its advanced features, including increased data rates, enhanced power efficiency, and innovative error correction mechanisms.

In this session, discover how Siemens’ Avery Verification IP (VIP) for HBM4 and LPDDR5/5X controllers provides a scalable and customizable solution for rigorous protocol compliance and performance testing. Learn how Rambus leveraged this VIP to verify their memory controller IP and subsystems, ensuring reliability and readiness for next-generation applications.