At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
LPDDR5T / LPDDR5X /
LPDDR5 Controller
The Rambus LPDDR5 Controller supporting LPDDR5T, LPDDR5X, LPDDR5 controller core is designed for use in applications requiring high memory throughput at low power including mobile, automotive, Internet of Things (IoT), laptop PCs, and edge networking devices.
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How the LPDDR5T/5X/5 Controller works
The LPDDR5 controller core accepts commands using a simple local interface and translates them to the command sequences required by LPDDR5 devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management logic to monitor the status of each LPDDR bank. Banks are only opened or closed when necessary, minimizing access delays.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
Add-On Cores such as an AXI Core Bus Interface, Multi-Port Front-End and In-Line ECC Core can be optionally delivered with the core. The core can be delivered fully integrated and verified with the target LPDDR5 PHY.
LPDDR5X: Delivering High Bandwidth and Power Efficiency
The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join us to learn which applications can benefit from using LPDDR memory.
Solution Offerings
- Support for all LPDDR5T/5X/5 devices
- Bank management logic monitors status of each bank
- Queue-based user interface with reordering scheduler
- Look-ahead activate, precharge, and auto-precharge logic
- Parity protection for all stored control registers
- PHY interface based on DFI 5.1 standard
- Each controller instance supports a single channel
- Multiple rank support (typically 2 or 4)
- Supports WCK:CK ratio 4:1
- Supports x16 mode
- Burst length BL16 and BL32
- Data bus inversion (DBI) feature (read and/or write)
- Supports masked write (MWR)
- Mode register write (MRW) and mode register read (MRR) functions
- Background ZQ calibration mode and command-based ZQ calibration mode
- Supports LPDDR5 speeds up to 9.6 Gbps/pin
- Supports all defined LPDDR5 channel densities (up to and including 32Gb, including non-binary densities)
- LPDDR5 bank architecture BG mode and 16B mode
- LPDDR5 per-bank refresh and all-bank refresh
- LPDDR5 refresh management
- LPDDR5 device self-refresh mode
- LPDDR5 device power-down mode
- Automatic generation of initialization and refresh sequences
- Built-in activity monitor
- Optional multi-burst capability
- Full set of add-on cores available
- Can be delivered fully integrated and verified with target LPDDR PHY
- Customization and integration services available
- Core (source code)
- Testbench (source code)
- Complete documentation
- Complete documentation
- Maintenance updates
- Customization
- SoC integration
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| LPDDR5T/5X/5 | 9.6 / 8.5 / 6.4 | Mobile, Automotive, IoT, Laptop PCs, Edge |
