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PCIe 6.0 Retimer Controller with CXL Support
PCI Express® (PCIe®) 6.0 links operating at 64 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on standard PCBs. Extending trace routing beyond this distance results in higher first bit error rates (FBER) and reduced link efficiency due to increased link recovery and retransmissions.
As new distributed architectures are deployed in data centers, greater flexibility is desired for chip placement including the need for longer trace lengths. Protocol-aware retimer chips can fully regenerate signals allowing board designers to extend reach and flexibly build various system topologies. The Rambus PCIe 6.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and area, and accelerates the time-to-market for PCIe 6.0 retimer chips.
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Product BriefHow the PCIe 6.0 Retimer Controller Works
The PCIe 6.0 Retimer Controller provides a highly optimized low-latency data path for signal regeneration. It supports retimer chip PHYs via PIPE 5.2/6.1 interfaces. The control plane interface is provided via CSR (AHB-lite). The PCIe 6.0 Retimer Controller is CXL protocol aware and supports links using 64 GT/s and lower data rates of PCIe.
The PCIe 6.0 Retimer Controller provides designers with highly configurable equalization algorithms and adaptive behaviors. Its advanced RAS features enable control, observation and debugging of the controller and PHYs in silicon. Further, it supports various PCIe clocking architectures.
Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1
The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the rapid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
Solution Offerings
Complete digital data path solution for PCIe 6.0 retimer chips
- Designed to the latest PCI Express 6.0 (64 GT/s), and capable of supporting 32.0, 16.0, 8.0, 5.0 and 2.5 GT/s link rates
- Supports x1, x2, x4, x8 and x16 link widths
- CXL aware and supports sync header bypass
- Supports PIPE 5.2/6.1 compatible PHYs
- Optimized data-path for low latency insertion
- Support for Figure of Merit and Up/Down PHY Equalization Feedback
- Highly configurable Equalization Algorithms with Adaptive Behaviors
- CSR (AHB-lite) control plane interface
- Advanced RAS features through pre-integrated XpressAgent debug monitor
- Supports SRIS, SRNS and common clock source modes
- Supports L0p power saving mode
IP Files
- Verilog RTL source code
- IPXACT files for registers
- Software API in C & Python for
- XpressAgent (debug monitor)
Documentation
- Retimer IP User Guide
- Getting Started Guide
Reference Designs
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project and DC constraintfiles (ASIC)
- Lint and CDC scripts
Advanced Design Integration Services:
- Integration of commercial and proprietary PCIe PHY IP
- Customization of the Controller IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
- Design/architecture review and consulting
