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Rambus XDR™ Memory Architecture Named 2008 DesignVision Winner

Memory architecture receives honors from prestigious International Engineering Consortium

LOS ALTOS, CALIFORNIA, UNITED STATES – 02/05/2008 – Rambus Inc. (NASDAQ: RMBS), one of the world’s premier technology licensing companies specializing in high-speed memory architectures, is pleased to announce that the International Engineering Consortium (IEC) has chosen the Rambus XDR™ memory architecture as the winner in the 2008 DesignVision Awards category for Semiconductors and ICs (IP). The IEC DesignVision Awards recognize technologies, applications, products, and services judged to be the most unique and beneficial to the industry.

“This year’s winners exemplify the highest level of innovation in today’s industry,” commented IEC Executive Vice President Roger Plummer. “We are pleased to congratulate Rambus for its XDR memory architecture, which received the 2008 DesignVision Award this week at DesignCon 2008.”

“We take great pride in advancing the state-of-the-art in innovative memory architectures and are honored to be recognized by the IEC,” said Kevin Donnelly, senior vice president of Engineering at Rambus. “The XDR architecture is a total memory system solution that enables blazing fast speeds with the fewest devices, making it ideal for computing and consumer electronics applications.”

Rambus recently announced that Toshiba has taken a license for the XDR memory architecture for its next-generation HDTV chipsets. In addition, Qimonda has begun shipping its first samples of XDR DRAM, and Elpida has begun shipping 4.8GHz XDR memory, the world’s fastest production DRAM.

Key components enabling the breakthrough performance of the XDR memory architecture are:

  • The XDR DRAM, a high-speed memory IC that turbo-charges standard CMOS DRAM cores with a high-speed interface capable of 4.0 GHz data rates providing up to 8 GB/s of bandwidth with a single device.
  • The XIO controller IO cell providing the same high-speed signaling capability found on the DRAM, but adding additional enhancements like FlexPhase™ technology that optimizes timing and eliminates the need for trace length matching.
  • The XMC memory controller, a fully synthesizable logical memory controller that is optimized to take advantage of innovations like Dynamic Point-to-Point which provides for capacity expansion while delivering the signal integrity benefits of point-to-point signaling.
  • The XCG clock generator providing the system clocks with four programmable outputs, guaranteed to meet the clocking requirements for the XIO and XDR DRAM devices.

About Rambus Inc.

Rambus is one of the world’s premier technology licensing companies specializing in the invention and design of high-speed memory architectures. Since its founding in 1990, the Company’s patented innovations, breakthrough technologies and renowned integration expertise have helped industry-leading chip and system companies bring superior products to market. Rambus’ technology and products solve customers’ most complex chip and system-level interface challenges enabling unprecedented performance in computing, communications and consumer electronics applications. Rambus licenses both its world-class patent portfolio as well as its family of leadership and industry-standard interface products. Headquartered in Los Altos, California, Rambus has regional offices in North Carolina, India, Germany, Japan, Korea and Taiwan. Additional information is available at www.rambus.com.

Rambus and the Rambus logo are registered trademarks of Rambus Inc. XDR and FlexPhase are trademarks of Rambus Inc. All other trade names are the service marks, trademarks, or registered trademarks of their respective owners.

Rambus Unveils Ground-breaking Terabyte Bandwidth Initiative

Advanced innovations to enable terabyte per second memory subsystems operating at a record 16Gbps

RAMBUS DEVELOPER FORUM – TOKYO, JAPAN – 11/28/2007 – Rambus Inc. (NASDAQ:RMBS), one of the world’s premier technology licensing companies specializing in high-speed memory architectures, today unveiled its Terabyte Bandwidth Initiative. This technology initiative includes the development of new memory signaling innovations that will facilitate blazing fast data rates of 16Gbps and enable a future memory architecture that can deliver an unprecedented terabyte per second (TB/s) of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC). With the technology developed through this initiative, Rambus will dramatically increase the data rate of memory above the current world’s fastest memory, the Rambus 4.8GHz XDR™ DRAM. Rambus will demonstrate a silicon test vehicle for its Terabyte Bandwidth Initiative today at RDF-Japan.

“We will drive memory signaling technology to performance levels that are an order of magnitude greater than what can be achieved today,” said Kevin Donnelly, senior vice president of engineering at Rambus Inc. “Continuing the Rambus tradition of innovation, our engineers and scientists have pioneered new technologies that will enable terabyte per second memory architectures for gaming, computing and consumer electronic systems of the next decade.”

Rambus’ Terabyte Bandwidth Initiative includes ground-breaking innovations for a new generation of memory systems, such as:

  • 32X data rate – 32 data bits per input clock cycle;
  • Fully Differential Memory Architecture (FDMA) – The industry’s first differential signaling for both data and command/address (C/A);
  • FlexLink™ C/A – The industry’s first full-speed, point-to-point C/A link.

The Terabyte Bandwidth Initiative is the latest in a long tradition of pioneering Rambus technology development programs. For more than seventeen years, Rambus engineering teams have developed the leadership innovations that enable faster signaling and advanced system designs. Committed to the advanced research and development of high-speed memory architectures, Rambus invests heavily in advanced circuit design, high-speed logic interfaces, low-power interface solutions, system engineering, signal integrity, verification, and testing. To date, Rambus engineers and scientists have developed innovations resulting in over 1000 issued and pending patents worldwide.

More information on the Terabyte Bandwidth Initiative and its innovations will be presented at the Rambus Developer Forum (RDF) in Tokyo, Japan (November 28-29, 2007, http://forum.rambus.co.jp/). Additional information on the Terabyte Bandwidth Initiative is also available at http://www.rambus.com/terabyte.

Rambus Introduces Memory Controller Interface Solution for Industry-standard DDR3 DRAM

RAMBUS DEVELOPER FORUM, HSINCHU, TAIWAN – 10/17/2007 – Rambus Inc. (NASDAQ:RMBS), one of the world’s premier technology licensing companies specializing in high-speed memory architectures, today announced the introduction of its memory controller interface solution for industry-standard DDR3 DRAM. The fully integrated hard macro cell provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz.

Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations, and network communications. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) chip.

“As signaling frequencies of mainstream DDR DRAMs continue to increase, the memory interfaces critical to system performance have become very challenging to design,” said Martin Scott, senior vice president of engineering at Rambus Inc. “Using our extensive signal integrity experience, we have architected a low-risk, highly optimized DDR3 memory controller interface that meets the performance requirements of both main memory and consumer applications.”

To ensure first-silicon success, a reliable system environment for high-volume production, and rapid in-system qualification, the Rambus DDR3 interface solution incorporates Rambus innovations such as:

  • FlexPhase™ timing adjustment circuits for precise on-chip data alignment with the clock
  • Calibrated output drivers
  • On-die termination
  • LabStation™ software environment for bring-up, characterization and validation of the DDR3 interface in the end-user application

Other key interface features include:

  • 800 to 1600 MHz data rates
  • Support for DDR3 and DDR2 signaling modes
  • On-chip phase-locked loop (PLL)
  • On-chip delay-locked loop (DLL)
  • Levelization support for fly-by command and address architecture
  • Rambus FlexPhase™ based in-PHY module that provides characterization and testing capability in the production system
  • Multi-drop bus and multi-rank module support for large capacity systems
  • Variable data bit-widths (8-, 16-, 32-, and 64-bit) with optional ECC support

Rambus DDR cells are supported by comprehensive system design and integration services that include a complete set of design models and integration tools, including GDSII database, timing models, layout verification netlists, gate-level models, place-and-route outline, and placement guidelines. Package design and system board layout services are also available. For more information about the Rambus DDR3 memory controller interface please visit www.rambus.com/ddr.

Elpida Introduces The World’s Fastest DRAM Based On The Rambus XDR Memory Architecture

4.8GHz XDR DRAM achieves 6x performance increase over industry-standard DDR2 DRAMs

LOS ALTOS, CALIFORNIA, UNITED STATES and TOKYO, JAPAN – 10/04/2007 – Elpida Memory, Inc. (Elpida) (Tokyo Stock Exchange Code 6665), Japan’s leading global supplier of Dynamic Random Access Memory (DRAM) and Rambus today introduced the industry’s fastest DRAM, the 512 Megabit (Mb), 4.8GHz XDR™ DRAM, based on Rambus’ XDR memory architecture. This latest addition to the XDR DRAM family provides an industry-leading data transfer rate of 9.6 Gigabytes per second (GB/s) with a single device, making it an ideal choice for high-performance, high-volume applications such as high-definition televisions (HDTV), gaming consoles, PCs, servers and workstations.

“The industry’s demand for memory bandwidth in next-generation products is growing rapidly as high-definition image data becomes more popular,” said Yoshitaka Kinoshita, officer for the Digital Consumer Division of Elpida Memory, Inc. “Working with Rambus on XDR DRAM, we can provide the most cost-effective, high-bandwidth memory solution to our customers.”

Elpida’s 512Mb, 4.8GHz XDR DRAM (Part number: EDX5116ADSE-5E-E) device is organized in 8-banks (x16/x8/x4 programmable), and with a 9.6GB/s data transfer rate delivers six times the peak bandwidth of industry-standard DDR2-800 memory devices. The 4.8GHz XDR device is manufactured using Elpida’s 70 nm process technology and is available in a 104-ball FBGA package. To support both high-speed and robust data transfer, XDR DRAM utilizes key enabling technologies built on patented Rambus innovations such as Differential Rambus Signaling Level (DRSL), which minimizes signal swing and noise; Octal Data Rate (ODR) technology which transfers eight bits of data on each clock cycle to achieve 4.8GHz operation with just a 600MHz clock; and FlexPhase™ circuit technology for precise on-chip data alignment with the clock. The 512Mb XDR DRAM device also features adaptive impedance matching, dynamic request scheduling and zero overhead refresh.

“Elpida’s 4.8GHz XDR DRAM is an excellent fit for consumer electronics applications requiring high bandwidth for 3-D graphics, high-definition image processing, and advanced multimedia,” said Sharon Holt, senior vice president of worldwide sales, licensing and marketing at Rambus. “Elpida is well established as a leading XDR DRAM supplier and we are proud to work with them to advance the roadmap for XDR to 4.8GHz, achieving the world’s fastest DRAM.”

XDR DRAM is an integral part of the XDR memory architecture, working seamlessly with the XDR Memory Controller (XMC), XDR IO controller interface cell (XIO), and the XDR Clock Generator (XCG) to enable unprecedented levels of memory performance while utilizing the fewest number of ICs. A single XDR DRAM device operating in x16 mode achieves a data transfer rate of 9.6GB/s. In comparison, it requires six DDR2-800 x16 devices to achieve an equivalent data rate.

Proven in high-volume applications, Rambus XDR memory solutions are backed by comprehensive engineering support services that range from chip design to system integration. XDR DRAM continues to provide an order of magnitude higher performance than today’s standard memories. For more information on the XDR memory architecture, as well as the next-generation XDR2 DRAM with micro-threading, please visit www.rambus.com/xdr.

Availability

Elpida’s 512Mb 4.8GHz XDR DRAM devices (Part number: EDX5116ADSE-5E-E) will be available for sampling in December 2007. Volume production is expected to begin in April 2008. A datasheet is available upon request.

About Elpida Memory, Inc.

Elpida Memory, Inc., (Tokyo Stock Exchange Code 6665), is a leading manufacturer of Dynamic Random Access Memory (DRAM) silicon chips. Our design, manufacturing, and sales operations are backed by our world class technology expertise. Our manufacturing facilities, Hiroshima Elpida Memory, Inc. (front-end processes) and Akita Elpida Memory, Inc. (back-end processes), utilize the most advanced manufacturing technologies available in the industry. Further, we have customer sales and marketing support offices in Japan, North America, Europe, Taiwan, Hong Kong and Singapore. Elpida’s portfolio of advanced products features such characteristics as high-density, high-speed, low power and small packing profiles. We provide applications across a wide range of areas, including high-end servers, mobile phones and digital consumer electronics. For more information about Elpida, please visit http://www.elpida.com.

About Rambus Inc.

Rambus is one of the world’s premier technology licensing companies specializing in the invention and design of high-speed chip architectures. Since its founding in 1990, the Company’s patented innovations, breakthrough technologies and renowned integration expertise have helped industry-leading chip and system companies bring superior products to market. Rambus’ technology and products solve customers’ most complex chip and system-level interface challenges enabling unprecedented performance in computing, communications and consumer electronics applications. Rambus licenses both its world-class patent portfolio as well as its family of leadership and industry-standard interface products. Headquartered in Los Altos, California, Rambus has regional offices in North Carolina, India, Germany, Japan, Korea and Taiwan. Additional information is available at www.rambus.com.

Rambus and the Rambus logo are registered trademarks of Rambus Inc. XDR and FlexPhase are trademarks of Rambus Inc. All other trade names are the service marks, trademarks, or registered trademarks of their respective owners.

Rambus And Cadence Collaborate And Deliver Fully Integrated And Independently Verified PCI Express Solutions

New offering combines best-of-breed design and verification IP for high-quality, low-risk, and simplified design integration

LOS ALTOS, CALIFORNIA, UNITED STATES – 09/04/2007 – Rambus Inc. (NASDAQ:RMBS), one of the world’s premier technology licensing companies specializing in high-speed memory architectures, and Cadence® Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced fully integrated and independently verified PCI Express® solutions. The two companies have collaborated and now offer highly adaptable PCI Express digital cores and PHY IP from Rambus, tightly integrated and verified with Cadence verification IP.

The result of the joint work provides SOC designers with an independently verified solution that seamlessly integrates Rambus’ design IP with the automated verification IP from Cadence. This solution helps shorten time to market with an efficient, predictable, and low-risk SOC design and verification to enhance the quality of the end product. In addition, the solution includes the Cadence Compliance Management System (CMS) featuring a PCI Express compliance verification plan (vPlan) and compliance tests, both of which have been specifically customized to the Rambus design IP. The CMS provides an automated plan and metric-driven solution to reach high levels of coverage without the need to develop tests. Based on the Cadence Incisive® Plan-to-Closure methodology, the offering allows customers to maximize design quality while minimizing protocol expertise and verification time.

“As a company developing cutting-edge technology, it is critical that we build our solutions on proven, tightly integrated technology,” said John F. Brown, vice president, Engineering at Tilera Corporation. “Using the combination of the Rambus configurable PCI Express Digital Controller with the independently developed verification IP from Cadence enables the rapid and successful IP integration we are looking for.”

“Through this collaboration, we are able to provide an ideal combination of Cadence verification IP and methodology expertise with Rambus design IP. This solution leverages the strengths of both companies, speeding up the IP integration process and increasing productivity and quality for customers,” said Steve Glaser, vice president of Marketing at Cadence’s Verification Division. “Designers will gain a higher degree of predictability with the functional coverage provided by the Rambus design-IP-specific CMS. The result gives our mutual customers confidence that they will get to market on schedule with a quality product.”

The PCI-SIG-compliant and interoperability-tested Rambus PCI Express solution has been implemented and shipped in numerous high-volume applications. Rambus digital core IP has adaptable application interfaces that minimize the amount of glue logic required for integration. Rambus PHY cells are delivered as complete serial communication cells, optimized for maximum production yield.

“Increasingly powerful computing and consumer electronics applications require IP solutions that are flexible and seamlessly integrate into our customers’ designs,” said Tim Messegee, vice president of Marketing at Rambus Inc. “With this collaboration, Cadence and Rambus continue our commitment to provide the market with superior integrated IP and EDA solutions that accelerate time to market and reduce design risk.”

Rambus Unveils Low Power Initiative For Multi-Gbps Platforms

Reduces power consumption by 3X over traditional serial link implementations

LOS ALTOS, CALIFORNIA, UNITED STATES – 02/12/2007 – Rambus Inc. (NASDAQ:RMBS), one of the world’s premier technology licensing companies specializing in high-speed memory architectures, today unveiled low power signaling technologies targeted at multi-Gbps platforms. Through this initiative, Rambus has achieved a 3X power reduction when compared to traditional serial link implementations while still delivering high performance. In its labs, Rambus demonstrated its low power technologies in a test transceiver that transferred more than 3,600 Terabits of data, the equivalent of the contents of nearly 100,000 standard-format DVDs, utilizing the power of only two standard AA batteries.

Rambus will be presenting a paper on the results of this initiative on February 14, 2007 at the International Solid State Circuits Conference (ISSCC) in San Francisco, CA.

“Rambus invests in technologies that provide the highest interface performance for a range of power envelopes,” said Kevin Donnelly, senior vice president of Engineering at Rambus. “This initiative further illustrates the innovative work our team is doing to help reduce power consumption without sacrificing performance. Working with our customers, we look forward to bringing these low power innovations to market.”

Rambus took a systems-level approach to reducing power in a multi-Gbps transceiver architecture. After analyzing the breakdown of power distribution in existing transceivers, Rambus developed a test chip in a 90nm foundry process technology that operates at 6.25 Gbps over a channel with -15dB of loss. The test transceiver dissipates 14 mW, resulting in a power-performance metric of 2.2 mW/Gbps. Rambus innovations, such as a low-offset receiver, low-swing voltage-mode transmitter, low-bandwidth CDR, and low-power phase rotator, enable significant power reduction over existing state-of-the-art transceiver designs.

The Rambus low power signaling technologies can be applied to future parallel bus and serial link products for use in power-sensitive compute and consumer applications.

About Rambus Inc.

Rambus is one of the world’s premier technology licensing companies specializing in the invention and design of high-speed chip architectures. Since its founding in 1990, the Company’s patented innovations, breakthrough technologies and renowned integration expertise have helped industry-leading chip and system companies bring superior products to market. Rambus’ technology and products solve customers’ most complex chip and system-level interface challenges enabling unprecedented performance in computing, communications and consumer electronics applications. Rambus licenses both its world-class patent portfolio as well as its family of leadership and industry-standard interface products. Headquartered in Los Altos, California, Rambus has regional offices in North Carolina, India, Germany, Japan, Korea and Taiwan. Additional information is available at www.rambus.com.

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