RAMBUS DEVELOPER FORUM, HSINCHU, TAIWAN – 10/17/2007 – Rambus Inc. (NASDAQ:RMBS), one of the world’s premier technology licensing companies specializing in high-speed memory architectures, today announced the introduction of its memory controller interface solution for industry-standard DDR3 DRAM. The fully integrated hard macro cell provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz.
Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations, and network communications. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) chip.
“As signaling frequencies of mainstream DDR DRAMs continue to increase, the memory interfaces critical to system performance have become very challenging to design,” said Martin Scott, senior vice president of engineering at Rambus Inc. “Using our extensive signal integrity experience, we have architected a low-risk, highly optimized DDR3 memory controller interface that meets the performance requirements of both main memory and consumer applications.”
To ensure first-silicon success, a reliable system environment for high-volume production, and rapid in-system qualification, the Rambus DDR3 interface solution incorporates Rambus innovations such as:
- FlexPhase™ timing adjustment circuits for precise on-chip data alignment with the clock
- Calibrated output drivers
- On-die termination
- LabStation™ software environment for bring-up, characterization and validation of the DDR3 interface in the end-user application
Other key interface features include:
- 800 to 1600 MHz data rates
- Support for DDR3 and DDR2 signaling modes
- On-chip phase-locked loop (PLL)
- On-chip delay-locked loop (DLL)
- Levelization support for fly-by command and address architecture
- Rambus FlexPhase™ based in-PHY module that provides characterization and testing capability in the production system
- Multi-drop bus and multi-rank module support for large capacity systems
- Variable data bit-widths (8-, 16-, 32-, and 64-bit) with optional ECC support
Rambus DDR cells are supported by comprehensive system design and integration services that include a complete set of design models and integration tools, including GDSII database, timing models, layout verification netlists, gate-level models, place-and-route outline, and placement guidelines. Package design and system board layout services are also available. For more information about the Rambus DDR3 memory controller interface please visit www.rambus.com/ddr.
