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PCIe 6.0 Retimer Controller with CXL Support
https://www.rambus.com/interface-ip/pci-express/pcie6-retimer-controller/PCIe 6.0 Retimer Controller with CXL Support Contact Us PCI Express® (PCIe®) 6.0 links operating at 64 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on standard PCBs. Extending trace routing beyond this distance results in higher first bit error rates (FBER) and reduced link efficiency due to […]
VESA DSC 1.2b Decoder for AMD Xilinx FPGAs Product Brief
https://go.rambus.com/vesa-dsc-1-2b-decoder-amd-xilinx-fpgas-product-brief#new_tabThe Rambus VESA® Display Stream Compression (DSC) decoder IP core for AMD Xilinx FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
VESA DSC 1.2b Decoder for Intel FPGAs Product Brief
https://go.rambus.com/vesa-dsc-1-2b-decoder-intel-fpgas-product-brief#new_tabThe Rambus VESA® Display Stream Compression (DSC) decoder IP core for Intel FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
HDMI 2.1 FEC Receiver Product Brief
https://go.rambus.com/hdmi-2-1-fec-rx-product-brief#new_tabThe HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/ de-mapping as specified by the HDMI 2.1 specification.
VDC-M 1.2 Encoder for AMD Xilinx FPGAs Product Brief
https://go.rambus.com/vesa-vdc-m-1-2-encoder-amd-xilinx-fpgas-product-brief#new_tabThe Rambus VESA VDC-M 1.2 Encoder IP Core for AMD Xilinx FPGAs implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.
HDMI 2.1 FEC Transmitter Product Brief
https://go.rambus.com/hdmi-2-1-fec-tx-product-brief#new_tabThe HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 specification.
VDC-M 1.2 Encoder for Intel FPGAs Product Brief
https://go.rambus.com/vesa-vdc-m-1-2-encoder-intel-fpgas-product-brief#new_tabThe Rambus VESA VDC-M 1.2 Encoder IP Core for Intel FPGAs implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.
DisplayPort 1.4 FEC Receiver Product Brief
https://go.rambus.com/displayport-1-4-fec-rx-product-brief#new_tabThe DisplayPortTM Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.
DisplayPort 1.4 FEC Transmitter for Automotive Displays Product Brief
https://go.rambus.com/displayport-1-4-fec-tx-asil-b-product-brief#new_tabThe DisplayPortTM Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. It contains additional safety features to detect and report transient or permanent faults in order to meet the high level of safety required by automotive applications. The IP core is ASIL-B ready, […]
DisplayPort 1.4 FEC Transmitter Product Brief
https://go.rambus.com/displayport-1-4-fec-tx-product-brief#new_tabThe DisplayPortTM Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.
