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Rambus Demonstrates Industry-first PCIe® 5.0 Digital Controller IP for FPGAs

https://www.rambus.com/rambus-demonstrates-industry-first-pcie5-digital-controller-ip-for-fpgas/

Highlights:  Achieves industry-first demonstration of 32 GT/s PCIe 5.0 Digital Controller IP operation on leading FPGA platforms Expands use models for FPGAs by enabling multi-instance, PCIe 5.0 switching and bridging at 32 GT/s speeds Enhances performance and capabilities of FPGAs for use in emulation and prototyping, test and measurement, aerospace and defense, and storage and […]

Rambus Design Summit Featured Speaker: Steven Woo

https://www.rambus.com/blogs/rambus-design-summit-featured-speaker-steven-woo/

Another week, another Rambus Design Summit wrap up! Over the coming weeks, we will be featuring sessions from RDS 2021 with key takeaways and speaker highlights. This week we are featuring… Session Topic: Emerging Compute Architectures for the Evolving Data Center Rambus fellow and distinguished inventor, Dr. Steven Woo, kicked off the Rambus Design Summit […]

CXL 2.0 Controller Product Brief

https://go.rambus.com/cxl2-controller-product-brief#new_tab

The Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard.

CXL 2.0 Controller with AXI Product Brief

https://go.rambus.com/cxl2-controller-axi-product-brief#new_tab

The Rambus Compute Express Link (CXL) 2.0 Controller with AXI leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. This controller offers support of the AMBA AXI, CPI and AMBA CXS-B protocol specifications.

PCIe 5.0 Controller with AXI Product Brief

https://go.rambus.com/pcie5-controller-axi-product-brief#new_tab

The Rambus PCIe 5.0 controller with AXI is designed for maximum performance and ease of use for PCI Express (PCIe) 5.0 applications. It comprises a complete SerDes subsystem with the Rambus PCIe 5.0 PHY or can integrate with PIPE 5.x-compliant 3rd-party PHYs. The controller is backwards compatible with PCIe 4.0, and 3.1/3.0.

PCIe 5.0 Multi-port Switch Product Brief

https://go.rambus.com/pcie5-multi-port-switch-product-brief#new_tab

The Rambus PCIe 5.0 Multi-port Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and up to 31 downstream ports.

PCIe 4.0 Controller with AXI Product Brief

https://go.rambus.com/pcie4-controller-axi-product-brief#new_tab

The Rambus PCIe 4.0 Controller with AXI is designed to achieve maximum PCI Express (PCIe) 4.0 performance with great design flexibility and ease of integration. It comprises a complete SerDes subsystem with the Rambus PCIe 4.0 PHY or can integrate with PIPE 4.2-compliant 3rd-party PHYs. The controller is backwards compatible with PCIe 3.1/3.0.

PCIe 3.1 Controller Product Brief

https://go.rambus.com/pcie3-controller-product-brief#new_tab

The Rambus PCIe 3.1 Controller is designed to achieve maximum PCI Express (PCIe) 3.1 performance with great design flexibility and ease of integration. The controller with the Rambus PCIe 3.1 PHY forms a comprehensive interface subsystem solution delivering high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

PCIe 3.1 Controller with AXI Product Brief

https://go.rambus.com/pcie3-controller-axi-product-brief#new_tab

The Rambus PCIe 3.1 Controller with AXI is designed to achieve maximum PCI Express (PCIe) 3.1 performance with great design flexibility and ease of integration. The controller with the Rambus PCIe 3.1 PHY forms a comprehensive interface subsystem solution delivering high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

PCIe 2.1 Controller Product Brief

https://go.rambus.com/pcie2-controller-product-brief#new_tab

The Rambus PCIe 2.1 Controller is designed to achieve maximum PCI Express (PCIe) 2.1 performance with great design flexibility and ease of integration. It is backward compatible with the PCIe 1.1 specification.

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