At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
ARC4-IP-44 ARC4 Stream Cipher Accelerators
The ARC4-IP-44 (EIP-44) is IP for accelerating the ARC4 stream cipher algorithm (used for legacy SSL & IPsec) up to 5 Gbps @ 600MHz. Designed for fast integration, low gate count and full transforms, the ARC4-IP-44 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.
ContactARC4 family of accelerators
Available in several configurations / performance grades
Library element for security packet engines
How the ARC4-IP-44 ARC4 Stream Cipher Accelerators work
The ARC4-IP-44 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Sustained performance for any object sizes ranges up to 5 Gbps depending on the configuration and area. Gate count is about 7K to 32K gates depending on the configuration.
Rambus also offers the AES-IP-39 that supports AES modes and can be provided with countermeasures including ones against side-channel attacks and fault injection attacks.
Anti-Tampering Technologies
The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.
ARC4-IP-44 Information
Key benefits:
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
Features:
- Wide bus interface (32-bit data, 128-bit keys) or 32-bit register interface
- Key sizes: 40 and 128 bits
- Fully synchronous design
Alternatives:
- AES-IP-32 AES ECB accelerators
- AES-IP-36 AES ECB/CBC/CTR accelerators
- AES-IP-37 AES Key Wrap accelerators
- AES-IP-38 AES XTS/GCM accelerators
- AES-IP-39 AES ECB/CBC/CTR/CCM/GCM accelerators
Introduction to Side-Channel Attacks
Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.
