At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
SCA Resistant Cores with DPA and FIA
Rambus SCA (Side Channel Attack) Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through DPA (Differential Power Analysis) and against sabotage through FIA (Fault Injection Attacks) when integrated into an SoC.
These superior performance cores are easily integrated into SoCs and FPGAs, providing robust side-channel resistance across different security and performance levels. The SCA Resistant Hardware Cores support industry standard classic cryptographic algorithms such as AES, 3DES, SM4, SHA-2, SHA-3, RSA, and ECC, as well as the quantum safe cryptographic algorithms ML-DSA and ML-KEM. In addition to DPA resistance, Rambus offers select accelerators with additional FIA (Fault Injection Attack) resistance. Select cores are Common Criteria and NIST FIPS 140-3 certified.
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Product Brief| Solution | Description |
|---|---|
| QSE-IP-86 DPA | Fast Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) with DPA |
| PKE-IP-85-DPA(-FIA) | Fast Public Key Engine with DPA or with DPA and FIA |
| AES-IP-3X-DPA(-FIA) | AES Authenticated Encryption Accelerator with DPA or with DPA and FIA |
| ICE-338-DPA | Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA |
| HMAC-SHA-256-DPA | HMAC SHA-2 engine, 224 & 256 Mode, DPA |
| HMAC-SHA-256-512-DPA | HMAC SHA-2 engine, 224, 256, 384 & 512 Mode, DPA |
| HMAC-IP-59-DPA | SHA-3 engine w/ HMAC, DPA SHA-3/SHAKE/cSHAKE/KMAC |
| SHA-IP-57-DPA | SHA-3 engine, w/o HMAC, DPA SHA-3/SHAKE/cSHAKE/KMAC |
How SCA Resistant cores with DPA and FIA work
The SCA Resistant Hardware cores offer chipmakers an easy-to integrate technology-independent soft-macro security solution with built-in side-channel resistance for cryptographic functions.
The SCA Resistant Hardware Cores implement highly-efficient digital SPA, DPA, CPA, DEMA, CEMA and TA countermeasures, delivering the highest level of performance and security while meeting silicon area and power budget targets.
The FIA countermeasures project against effects of various (non-) invasive Fault Injection Attacks, such as voltage, clock, temperature, glitch, light, laser and EM attacks.
The soft macro SCA cores improve time-to-market through being SCA pre-validated, avoiding unpredictable and time-consuming validation cycles They are easy to integrate into various SoC and FPGA architectures and development flows, and are all designed to maximize performance versus silicon area requirements. The Rambus IP cores pass all NIST CAVP vectors.
Introduction to Side-Channel Attacks
Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.
Solution Offerings
- Superior performance cryptographic cores optimized for performance, area, and security applications
- AES-32 cores with SCA protection run at 1 clock cycle per AES round, outperforming any existing solution by a factor of 2
- Protect leakage of secret keys while in use, providing orders of magnitude higher protection than standard cores
- Extensively validated using the Test Vector Leakage Assessment (TVLA) methodology revealing no leakage beyond 100 million traces
- Protected against SPA, DPA, DEMA, CPA, CEMA and TA SCA attacks
- Protect against effects of various (non-)invasive Fault Injection Attacks, such as voltage, clock, temperature, glitch, light, laser and EM attacks
- Digital countermeasures: portable to any FPGA or ASIC technology
- Common Criteria certified
- NIST CAVP certified
- SCA (DPA & FIA) Resistant Core in Verilog RTL Source code
- SDC constraints synthesis input for FPGA or ASIC synthesis
- Documentation
- Test bench and vectors
- Support and integration assistance
- TVLA Report
Protecting Electronic Systems from Side-Channel Attacks
Side-channel attacks comprise a wide range of techniques including Differential Power Analysis, Simple Power Analysis, Simple Electromagnetic Analysis, Differential Electromagnetic Analysis, Correlation Power Analysis and Correlation Electromagnetic Analysis. An effective layer of side-channel countermeasures should therefore be implemented via hardware (DPA resistant cores), software (DPA resistant libraries) or both. After layered countermeasures have been implemented, systems should be carefully evaluated to confirm the cessation of sensitive side-channel leakage.
Inventions
DPA Countermeasures
DPA Countermeasures are fundamental techniques for protecting against Differential Power Analysis (DPA) and related side-channel attacks. Consisting of a broad range of software, hardware, and protocol techniques, DPA Countermeasures include reducing leakage, introducing amplitude and temporal noise, balancing hardware and software, incorporating randomness, and implementing protocol level countermeasures.
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