At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
In this episode of Ask the Experts, we discuss HBM4 with Nidish Kamath, director of product management for memory interface IP at Rambus.
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In this episode of Ask the Experts, we discuss the latest PCI Express (PCIe) developments with Lou Ternullo, senior director of product management at Rambus.
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In this episode of Ask the Experts, we discuss HBM3E memory with Nidish Kamath, director of product management for memory interface IP at Rambus, and Frank Ferro, group director of memory and storage IP at Cadence.
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AI is a rapidly evolving space. With the meteoric rise of generative AI applications in the past year, we are now firmly in the era of AI 2.0. This is characterized by large language models that place AI into the hands of millions of consumers and enterprises offering limitless possibilities for creativity and innovation. We recently interviewed Dr. Steven Woo, fellow and distinguished inventor at Rambus Labs, to find out more about AI 2.0 and the key technologies that will shape it going forward.
From concept to production, designing a PCIe 5.0 device requires a long development cycle owed largely to heavy efforts on verification and validation.
Today, a large collection of tools enable simulation to find bugs during the verification process or to generate PCIe transactions to validate the device. However, these tools are not enough to provide 100% confidence before a device can go to production for one main reason: all these tests and simulations were not done in a real hardware environment.
That’s why Rambus created INSPECTOR for PCIe 5.0 Interposer Cards.
Check this video to understand how Inspector can help for Diagnostic, Testing, Exercising and Debug of PCIe 5.0 Devices.
In this video, we demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel’s Pre-Production Xeon processor as a host, connected to an FPGA board, instantiating Rambus’ CXL Controller and CXL.mem test design.
